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ASPDAC
2005
ACM
133views Hardware» more  ASPDAC 2005»
15 years 6 months ago
A novel O(n) parallel banker's algorithm for System-on-a-Chip
This paper proposes a novel O(n) Parallel Banker’s Algorithm (PBA) with a best-case run-time of O(1), reduced from an ¢¤£¦¥¨§© run-time complexity of the original Ban...
Jaehwan John Lee, Vincent John Mooney III
SBACPAD
2007
IEEE
110views Hardware» more  SBACPAD 2007»
15 years 10 months ago
Architectural Breakdown of End-to-End Latency in a TCP/IP Network
Adoption of the 10GbE Ethernet standard has been impeded by two important performance-oriented considerations: 1) processing requirements of common protocol stacks and 2) end-to-e...
Steen Larsen, Parthasarathy Sarangam, Ram Huggahal...
183
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ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
15 years 9 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
CODES
2007
IEEE
15 years 10 months ago
Performance modeling for early analysis of multi-core systems
Performance analysis of microprocessors is a critical step in defining the microarchitecture, prior to register-transfer-level (RTL) design. In complex chip multiprocessor systems...
Reinaldo A. Bergamaschi, Indira Nair, Gero Dittman...
DAC
2010
ACM
15 years 8 months ago
Processor virtualization and split compilation for heterogeneous multicore embedded systems
Complex embedded systems have always been heterogeneous multicore systems. Because of the tight constraints on power, performance and cost, this situation is not likely to change a...
Albert Cohen, Erven Rohou