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ISCAS
1995
IEEE
91views Hardware» more  ISCAS 1995»
15 years 1 months ago
An FPGA Based Reconfigurable Coprocessor Board Utilizing a Mathematics of Arrays
Abstract -- Work in progress at the University of Missouri-Rolla on hardware assists for high performance computing is presented. This research consists of a novel field programmab...
W. Eatherton, J. Kelly, T. Schiefelbein, H. Pottin...
FPL
2009
Springer
117views Hardware» more  FPL 2009»
15 years 2 months ago
Data parallel FPGA workloads: Software versus hardware
Commercial soft processors are unable to effectively exploit the data parallelism present in many embedded systems workloads, requiring FPGA designers to exploit it (laboriously) ...
Peter Yiannacouras, J. Gregory Steffan, Jonathan R...
ISCA
2007
IEEE
146views Hardware» more  ISCA 2007»
15 years 4 months ago
Hardware atomicity for reliable software speculation
Speculative compiler optimizations are effective in improving both single-thread performance and reducing power consumption, but their implementation introduces significant compl...
Naveen Neelakantam, Ravi Rajwar, Suresh Srinivas, ...
CODES
2003
IEEE
15 years 3 months ago
Design space exploration of a hardware-software co-designed GF(2m) galois field processor for forward error correction and crypt
This paper describes a hardware-software co-design approach for flexible programmable Galois Field Processing for applications which require operations over GF(2m ), such as RS an...
Wei Ming Lim, Mohammed Benaissa
ERSA
2006
86views Hardware» more  ERSA 2006»
14 years 11 months ago
GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs
In reconfigurable systems, reconfiguration latency has a significant impact on the system performance. In this work, a temporal partitioning algorithm is presented to partition da...
Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedi...