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IPPS
1997
IEEE
15 years 2 months ago
A Reliable Hardware Barrier Synchronization Scheme
Barrier synchronization is a crucial operation for parallel systems. Many schemes have been proposed in the literature to achieve fast barrier synchronization through software, ha...
Rajeev Sivaram, Craig B. Stunkel, Dhabaleswar K. P...
ARC
2010
Springer
186views Hardware» more  ARC 2010»
15 years 1 months ago
Application-Specific Signatures for Transactional Memory in Soft Processors
As reconfigurable computing hardware and in particular FPGA-based systems-on-chip comprise an increasing number of processor and accelerator cores, supporting sharing and synchroni...
Martin Labrecque, Mark Jeffrey, J. Gregory Steffan
ANCS
2007
ACM
15 years 1 months ago
Frame shared memory: line-rate networking on commodity hardware
Network processors provide an economical programmable platform to handle the high throughput and frame rates of modern and next-generation communication systems. However, these pl...
John Giacomoni, John K. Bennett, Antonio Carzaniga...
EUC
2007
Springer
15 years 1 months ago
Parallel Network Intrusion Detection on Reconfigurable Platforms
With the wide adoption of internet into our everyday lives, internet security becomes an important issue. Intrusion detection at the network level is an effective way of stopping m...
Chun Xue, Zili Shao, Meilin Liu, Qingfeng Zhuge, E...
FPL
2009
Springer
113views Hardware» more  FPL 2009»
15 years 2 months ago
Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays
Spatially-tiled architectures, such as Coarse-Grained Reconfigurable Arrays (CGRAs), are powerful architectures for accelerating applications in the digital-signal processing, em...
Brian Van Essen, Aaron Wood, Allan Carroll, Stephe...