9974 search results - page 115 / 1995 » Software Interconnection Models |
88
Voted
DATE
2010
IEEE
15 years 6 months ago
2010
IEEE
: Scaling down in very deep submicron (VDSM) technologies increases the delay, power consumption of on-chip interconnects, while the reliability and yield decrease. In high perform...
FPGA
1997
ACM
15 years 6 months ago
1997
ACM
ct High-capacity FPGAs pose device architects with a variety of problems. The most obvious of these problems is interconnect capacity. Others include interconnect performance, cloc...
137
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PROFES
2001
Springer
15 years 6 months ago
2001
Springer
In this paper, we report from an experiment which compared the E3 PML with respect to the standard modelling language IDEF0 for the purpose of model construction. The experiment ha...
116
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ICCAD
2002
IEEE
15 years 10 months ago
2002
IEEE
As the scale of system integration continues to grow, the on-chip communication becomes the ultimate bottleneck of system performance and the primary determinant of system archite...
DATE
2003
IEEE
15 years 7 months ago
2003
IEEE
In today’s deep-submicron designs, the interconnect delays contribute an increasing part to the overall performance of an implementation. Particularly when targeting field prog...