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SLIP
2006
ACM
15 years 3 months ago
Generation of design guarantees for interconnect matching
Manufacturable design requires matching of interconnects which have equal nominal dimensions. New design rules are projected to bring guarantee rules for interconnect matching. In...
Andrew B. Kahng, Rasit Onur Topaloglu
DATE
2008
IEEE
204views Hardware» more  DATE 2008»
15 years 3 months ago
Deep Submicron Interconnect Timing Model with Quadratic Random Variable Analysis
Shrinking feature sizes and process variations are of increasing concern in modern technology. It is urgent that we develop statistical interconnect timing models which are harmon...
Jun-Kuei Zeng, Chung-Ping Chen
ICCD
2002
IEEE
140views Hardware» more  ICCD 2002»
15 years 6 months ago
Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model
— In this paper, we present a new interconnect delay model called Fitted Elmore delay (FED). FED is generated by approximating Hspice delay data using a curve fitting technique....
Arif Ishaq Abou-Seido, Brian Nowak, Chris C. N. Ch...
ISLPED
2000
ACM
68views Hardware» more  ISLPED 2000»
15 years 1 months ago
Noise-aware power optimization for on-chip interconnect
Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultra deep sub-micron processes. We characterize the c...
Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L....
ICCAD
2004
IEEE
139views Hardware» more  ICCAD 2004»
15 years 6 months ago
Fast simulation of VLSI interconnects
This paper introduces an efficient and accurate interconnect simulation technique. A new formulation for typical VLSI interconnect structures is proposed which, in addition to pr...
Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakri...