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ICCAD
2003
IEEE
123views Hardware» more  ICCAD 2003»
15 years 6 months ago
Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion
In this paper, we study the full-chp interconnect power modeling. ,We show that repeater,insertion is no longer sufficient to achievethe targetfrequencies specifiedhy ITRS, and de...
Weiping Liao, Lei He
ISCAS
2007
IEEE
144views Hardware» more  ISCAS 2007»
15 years 3 months ago
Quasi-Resonant Interconnects: A Low Power Design Methodology
— Design and analysis guidelines for resonant interconnect networks are presented in this paper. The methodology focuses on developing an accurate analytic distributed model of t...
Jonathan Rosenfeld, Eby G. Friedman
84
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ICCD
2003
IEEE
113views Hardware» more  ICCD 2003»
15 years 2 months ago
Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity
As the technology is shrinking toward 50 nm and the working frequency is going into multi gigahertz range, the effect of interconnects on functionality and performance of system-o...
Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nour...
ICCAD
2002
IEEE
98views Hardware» more  ICCAD 2002»
15 years 6 months ago
On-chip interconnect modeling by wire duplication
In this paper, we present a novel wire duplication-based interconnect modeling technique. The proposed modeling technique exploits the sparsity of the L 1 matrix, where L is the ...
Guoan Zhong, Cheng-Kok Koh, Kaushik Roy
ICCAD
1996
IEEE
129views Hardware» more  ICCAD 1996»
15 years 1 months ago
Accurate interconnect modeling: towards multi-million transistor chips as microwave circuits
-- In this tutorial we discuss concepts and techniques for the accurate and efficient modeling and extraction of interconnect parasitics in VLSI designs. Due toincreasing operating...
N. P. van der Meijs, T. Smedes