9974 search results - page 30 / 1995 » Software Interconnection Models |
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
— As clock frequencies exceed giga-Hertz, the extra power loss due to conductor surface roughness in interconnects and packagings is more evident and thus demands a proper accou...
80
Voted
ISQED
2007
IEEE
15 years 3 months ago
2007
IEEE
In this paper, we propose a new approach to enforcing the passivity of a reduced system of general passive linear time invariant circuits. Instead of making the reduced models pas...
ICCAD
2008
IEEE
15 years 6 months ago
2008
IEEE
— As Double Patterning Technology (DPT) becomes the only solution for 32-nm lithography process, we need to investigate how DPT affects the performance of a chip. In this paper, ...
ICCAD
1997
IEEE
15 years 1 months ago
1997
IEEE
In this paper, we study the interconnect layout optimization problem under a higher-order RLC model to optimize not just delay, but also waveform for RLC circuits with non-monoton...
DATE
2010
IEEE
15 years 2 months ago
2010
IEEE
—1 In this paper we present a stochastic model order reduction technique for interconnect extraction in the presence of process variabilities, i.e. variation-aware extraction. It...