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ASPDAC
2006
ACM
122views Hardware» more  ASPDAC 2006»
15 years 7 months ago
IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults
– We propose an interconnect diagnosis scheme based on Oscillation Ring test methodology for SOC design with heterogeneous cores. The target fault models are delay faults and cro...
Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, ...
ALC
1997
15 years 2 months ago
Synthesising interconnections
In the context of the modular and incremental development of complex systems, viewed as interconnections of interacting components, new dimensions and new problems arise in the ca...
José Luiz Fiadeiro, Antónia Lopes, T...
GLOBECOM
2008
IEEE
15 years 2 months ago
Investigating the Influence of Market Shares on Interconnection Settlements
— This paper investigates the role of providers’ market shares for consumers and websites on interconnection settlements between networks. We proposed to differentiate traffic ...
Ruzana Davoyan, Jörn Altmann
FPGA
2008
ACM
145views FPGA» more  FPGA 2008»
15 years 3 months ago
FPGA interconnect design using logical effort
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong
IOLTS
2003
IEEE
133views Hardware» more  IOLTS 2003»
15 years 6 months ago
Power Consumption of Fault Tolerant Codes: the Active Elements
On-chip global interconnections in very deep submicron technology (VDSM) ICs are becoming more sensitive and prone to errors caused by power supply noise, crosstalk noise, delay v...
Daniele Rossi, Steven V. E. S. van Dijk, Richard P...