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DATE
2003
IEEE
101views Hardware» more  DATE 2003»
15 years 6 months ago
Combined FDTD/Macromodel Simulation of Interconnected Digital Devices
Behavioral models of digital devices based on Radial Basis Functions (RBF) are incorporated into a Finite-Difference Time-Domain (FDTD) solver for full-wave analysis of interconne...
Stefano Grivet-Talocia, Igor S. Stievano, Ivan A. ...
VLSID
1999
IEEE
93views VLSI» more  VLSID 1999»
15 years 5 months ago
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...
Noel Menezes, Chung-Ping Chen
ISQED
2003
IEEE
133views Hardware» more  ISQED 2003»
15 years 6 months ago
Impact of Interconnect Pattern Density Information on a 90nm Technology ASIC Design Flow
The importance of an interconnect pattern density model in ASIC design flow for a 90nm technology is presented. It is shown that performing the timing analysis at the worst-case c...
Payman Zarkesh-Ha, S. Lakshminarayann, Ken Doniger...
ISCC
1999
IEEE
111views Communications» more  ISCC 1999»
15 years 5 months ago
Structure and Performance Evaluation of a Replicated Banyan Network Based ATM Switch
Banyan networks are commonly used as interconnection structures in ATM switches. This paper is concerned with the replication technique which was applied to the standard banyan ne...
Moustafa A. Youssef, Mohamed N. El-Derini, Hussein...
DAC
1999
ACM
15 years 6 months ago
Buffer Insertion with Accurate Gate and Interconnect Delay Computation
Buffer insertion has become a critical step in deep submicron design, and several buffer insertion/sizing algorithms have been proposed in the literature. However, most of these m...
Charles J. Alpert, Anirudh Devgan, Stephen T. Quay