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ASPDAC
2006
ACM
97views Hardware» more  ASPDAC 2006»
15 years 7 months ago
Wire sizing with scattering effect for nanoscale interconnection
—For nanoscale interconnection, the scattering effect will soon become prominent due to scaling. It will increase the effective resistivity and thus interconnection delay signifi...
Sean X. Shi, David Z. Pan
VLSID
2000
IEEE
102views VLSI» more  VLSID 2000»
15 years 6 months ago
Inductance Characterization of Small Interconnects Using Test-Signal Method
The test signal method can be used to measure and model inductance parameters (self and mutual) of a very small interconnect especially in highdensity IC’s by using a test signa...
Jeegar Tilak Shah, Madhav P. Desai, Sugata Sanyal
GLVLSI
2003
IEEE
186views VLSI» more  GLVLSI 2003»
15 years 7 months ago
A fast simulation approach for inductive effects of VLSI interconnects
Modeling on-chip inductive effects for interconnects of multigigahertz microprocessors remains challenging. SPICE simulation of these effects is very slow because of the large num...
Xiaoning Qi, Goetz Leonhardt, Daniel Flees, Xiao-D...
3DIC
2009
IEEE
146views Hardware» more  3DIC 2009»
15 years 8 months ago
A routerless system level interconnection network for 3D integrated systems
- This paper describes a new architectural paradigm for fully connected, single-hop system level interconnection networks. The architecture is scalable enough to meet the needs of ...
Kelli Ireland, Donald M. Chiarulli, Steven P. Levi...
ICCAD
1997
IEEE
94views Hardware» more  ICCAD 1997»
15 years 5 months ago
PRIMA: passive reduced-order interconnect macromodeling algorithm
— This paper describes an algorithm for generating provably passive reduced-order N-port models for RLC interconnect circuits. It is demonstrated that, in addition to macromodel ...
Altan Odabasioglu, Mustafa Celik, Lawrence T. Pile...