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ASPDAC
2005
ACM
101views Hardware» more  ASPDAC 2005»
15 years 3 months ago
A wideband hierarchical circuit reduction for massively coupled interconnects
— We develop a realizable circuit reduction to generate the interconnect macro-model for parasitic estimation in wideband applications. The inductance is represented by VPEC (vec...
Hao Yu, Lei He, Zhenyu Qi, Sheldon X.-D. Tan
ICPP
1992
IEEE
15 years 5 months ago
Adaptive Binary Sorting Schemes and Associated Interconnection Networks
Many routing problems in parallel processing, such as concentration and permutation problems, can be cast as sorting problems. In this paper, we consider the problem of sorting on ...
Minze V. Chien, A. Yavuz Oruç
VLSID
2003
IEEE
183views VLSI» more  VLSID 2003»
16 years 2 months ago
Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy
We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI circuit.The problem can be restated as a combined buffer insertion, buffer siz...
Vani Prasad, Madhav P. Desai
IPPS
2009
IEEE
15 years 8 months ago
Deadlock prevention by turn prohibition in interconnection networks
Abstract—In this paper we consider the problem of constructing minimal cycle-breaking sets of turns for graphs that model communication networks, as a method to prevent deadlocks...
Lev B. Levitin, Mark G. Karpovsky, Mehmet Mustafa
HOTI
2005
IEEE
15 years 7 months ago
A Scalable, Self-Routed, Terabit Capacity, Photonic Interconnection Network
We present SPINet (Scalable Photonic Integrated Network), an optical switching architecture particularly designed for photonic integration. The performance of SPINet-based network...
Assaf Shacham, Benjamin G. Lee, Keren Bergman