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HASE
2008
IEEE
15 years 8 months ago
Using Multi-Level Security Annotations to Improve Software Assurance
Current annotation technologies suffer from poor coverage over the development process phases, limited support for the broad scope of the security requirement types and inadequate...
Eryk Kylikowski, Riccardo Scandariato, Wouter Joos...
DAC
2005
ACM
16 years 2 months ago
Segregation by primary phase factors: a full-wave algorithm for model order reduction
Existing Full-wave Model Order Reduction (FMOR) approaches are based on Expanded Taylor Series Approximations (ETAS) of the oscillatory full-wave system matrix. The accuracy of su...
Thomas J. Klemas, Luca Daniel, Jacob K. White
ISCAS
2006
IEEE
99views Hardware» more  ISCAS 2006»
15 years 7 months ago
MIMO interconnects order reductions by using the global Arnoldi algorithm
— We propose the global Arnoldi algorithm for MIMO RLCG interconnect model order reductions. This algorithm is an extension of the standard Arnoldi algorithm for systems with mul...
Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng
PATMOS
2005
Springer
15 years 7 months ago
Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing
Early circuit performance estimation and easy-to-apply methods for minimum-delay gate sizing are needed, in order to enhance circuit’s performance and to increase designers’ pr...
Giorgos Dimitrakopoulos, Dimitris Nikolos
DATE
2003
IEEE
154views Hardware» more  DATE 2003»
15 years 7 months ago
Packetized On-Chip Interconnect Communication Analysis for MPSoC
Interconnect networks play a critical role in shared memory multiprocessor systems-on-chip (MPSoC) designs. MPSoC performance and power consumption are greatly affected by the pac...
Terry Tao Ye, Luca Benini, Giovanni De Micheli