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HPCA
1995
IEEE
15 years 1 months ago
Software Cache Coherence for Large Scale Multiprocessors
Shared memory is an appealing abstraction for parallel programming. It must be implemented with caches in order toperform well, however, and caches require a coherence mechanism t...
Leonidas I. Kontothanassis, Michael L. Scott
AAAI
1994
14 years 11 months ago
Recovering Software Specifications with Inductive Logic Programming
We consider using machine learning techniques to help understand a large software system. In particular, we describe how learning techniques can be used to reconstruct abstract Da...
William W. Cohen
EUROSYS
2007
ACM
15 years 7 months ago
STMBench7: a benchmark for software transactional memory
Software transactional memory (STM) is a promising technique for controlling concurrency in modern multi-processor architectures. STM aims to be more scalable than explicit coarse...
Rachid Guerraoui, Michal Kapalka, Jan Vitek
FCCM
2011
IEEE
220views VLSI» more  FCCM 2011»
14 years 1 months ago
Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems
— This paper describes an architecture and FPGA synthesis toolchain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide ...
Manish Arora, Jack Sampson, Nathan Goulding-Hotta,...
ICSE
2012
IEEE-ACM
13 years 11 days ago
Debugger Canvas: Industrial experience with the code bubbles paradigm
—At ICSE 2010, the Code Bubbles team from Brown University and the Code Canvas team from Microsoft Research presented similar ideas for new user experiences for an integrated dev...
Robert DeLine, Andrew Bragdon, Kael Rowan, Jens Ja...