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ISCA
2000
IEEE
107views Hardware» more  ISCA 2000»
15 years 1 months ago
A fully associative software-managed cache design
As DRAM access latencies approach a thousand instructionexecution times and on-chip caches grow to multiple megabytes, it is not clear that conventional cache structures continue ...
Erik G. Hallnor, Steven K. Reinhardt
ASPLOS
2010
ACM
15 years 20 days ago
Micro-pages: increasing DRAM efficiency with locality-aware data placement
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
Kshitij Sudan, Niladrish Chatterjee, David Nellans...
LCTRTS
2007
Springer
15 years 3 months ago
Scratchpad allocation for data aggregates in superperfect graphs
Existing methods place data or code in scratchpad memory, i.e., SPM by either relying on heuristics or resorting to integer programming or mapping it to a graph coloring problem. ...
Lian Li 0002, Quan Hoang Nguyen, Jingling Xue
POPL
2009
ACM
15 years 10 months ago
Feedback-directed barrier optimization in a strongly isolated STM
Speed improvements in today's processors have largely been delivered in the form of multiple cores, increasing the importance of ions that ease parallel programming. Software...
Nathan Grasso Bronson, Christos Kozyrakis, Kunle O...
JSS
2007
105views more  JSS 2007»
14 years 9 months ago
Composing pattern-based components and verifying correctness
Designing large software systems out of reusable components has become increasingly popular. Although liberal composition of reusable components saves time and expense, many exper...
Jing Dong, Paulo S. C. Alencar, Donald D. Cowan, S...