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ISCA
2011
IEEE
229views Hardware» more  ISCA 2011»
14 years 3 months ago
TLSync: support for multiple fast barriers using on-chip transmission lines
As the number of cores on a single-chip grows, scalable barrier synchronization becomes increasingly difficult to implement. In software implementations, such as the tournament ba...
Jungju Oh, Milos Prvulovic, Alenka G. Zajic
TON
2012
13 years 2 months ago
Latency Equalization as a New Network Service Primitive
—Multiparty interactive network applications such as teleconferencing, network gaming, and online trading are gaining popularity. In addition to end-to-end latency bounds, these ...
Minlan Yu, Marina Thottan, Li (Erran) Li
DAC
2012
ACM
13 years 2 months ago
Chisel: constructing hardware in a Scala embedded language
In this paper we introduce Chisel, a new hardware construction language that supports advanced hardware design using highly parameterized generators and layered domain-specific h...
Jonathan Bachrach, Huy Vo, Brian Richards, Yunsup ...
ICDE
2007
IEEE
125views Database» more  ICDE 2007»
16 years 1 months ago
Collecting and Maintaining Just-in-Time Statistics
Traditional DBMSs decouple statistics collection and query optimization both in space and time. Decoupling in time may lead to outdated statistics. Decoupling in space may cause s...
Amr El-Helw, Ihab F. Ilyas, Wing Lau, Volker Markl...
HPCA
2009
IEEE
16 years 12 days ago
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
Niti Madan, Li Zhao, Naveen Muralimanohar, Anirudd...