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DATE
2003
IEEE
132views Hardware» more  DATE 2003»
15 years 9 months ago
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design
On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip co...
Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung C...
150
Voted
DEXAW
2003
IEEE
122views Database» more  DEXAW 2003»
15 years 9 months ago
A Framework for Self-Optimizing Grids Using P2P Components
We present the framework of a new grid architecture based on the peer-to-peer and the component paradigms. In our architecture, several peer-to-peer components are loosely coupled...
Florian Schintke, Thorsten Schütt, Alexander ...
120
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DFT
2003
IEEE
100views VLSI» more  DFT 2003»
15 years 9 months ago
Scan-Based BIST Diagnosis Using an Embedded Processor
For system-on-chip designs that contain an embedded processor, this paper present a software based diagnosis scheme that can make use of the processor to aid in diagnosis in a sca...
Kedarnath J. Balakrishnan, Nur A. Touba
118
Voted
DISCEX
2003
IEEE
15 years 9 months ago
DynaBone: Dynamic Defense Using Multi-layer Internet Overlays
1 Typically, individual DDOS solutions trade service level for security, resulting in overall decreased service performance. Further, each single DDOS solution presents a target fo...
Joseph D. Touch, Gregory G. Finn, Yu-Shun Wang, La...
149
Voted
DSN
2003
IEEE
15 years 9 months ago
Evaluation of Fault Handling of the Time-Triggered Architecture with Bus and Star Topology
Arbitrary faults of a single node in a time-triggered architecture (TTA) bus topology system may cause error propagation to correct nodes and may lead to inconsistent system state...
Astrit Ademaj, Håkan Sivencrona, Günthe...
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