39 search results - page 7 / 8 » Software Pipelining for Coarse-Grained Reconfigurable Instru... |
177
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CODES
2003
IEEE
15 years 11 months ago
2003
IEEE
This paper describes a hardware-software co-design approach for flexible programmable Galois Field Processing for applications which require operations over GF(2m ), such as RS an...
134
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DSN
2002
IEEE
15 years 10 months ago
2002
IEEE
The architecture and implementation of the LEON-FT processor is presented. LEON-FT is a fault-tolerant 32-bit processor based on the SPARC V8 instruction set. The processors toler...
135
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DAC
1999
ACM
16 years 6 months ago
1999
ACM
Abstract { This paper presents the machine description language LISA for the generation of bitand cycle accurate models of DSP processors. Based on a behavioral operation descripti...
186
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CGO
2003
IEEE
15 years 11 months ago
2003
IEEE
A dynamic binary translation system for a co-designed virtual machine is described and evaluated. The underlying hardware directly executes an accumulator-oriented instruction set...
167
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DATE
2010
IEEE
15 years 10 months ago
2010
IEEE
—In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communicati...