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» Software Reliability Engineering: A Roadmap
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CODES
2003
IEEE
15 years 2 months ago
A modular simulation framework for architectural exploration of on-chip interconnection networks
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
Tim Kogel, Malte Doerper, Andreas Wieferink, Raine...
CCS
2003
ACM
15 years 2 months ago
MECA: an extensible, expressive system and language for statically checking security properties
This paper describes a system and annotation language, MECA, for checking security rules. MECA is expressive and designed for checking real systems. It provides a variety of pract...
Junfeng Yang, Ted Kremenek, Yichen Xie, Dawson R. ...
IWMM
2010
Springer
173views Hardware» more  IWMM 2010»
15 years 2 months ago
CETS: compiler enforced temporal safety for C
Temporal memory safety errors, such as dangling pointer dereferences and double frees, are a prevalent source of software bugs in unmanaged languages such as C. Existing schemes t...
Santosh Nagarakatte, Jianzhou Zhao, Milo M. K. Mar...
ICEIS
2000
IEEE
15 years 2 months ago
Architectural Considerations with Distributed Computing
We understand distributed systems as a collection of distributed computation resources that work together as one harmonious system. It is the great achievement of computer network...
Yibing Wang, Robert M. Hyatt, Barrett R. Bryant
JACM
2002
163views more  JACM 2002»
14 years 9 months ago
Formal verification of standards for distance vector routing protocols
We show how to use an interactive theorem prover, HOL, together with a model checker, SPIN, to prove key properties of distance vector routing protocols. We do three case studies: ...
Karthikeyan Bhargavan, Davor Obradovic, Carl A. Gu...