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IISWC
2008
IEEE
15 years 4 months ago
Accelerating multi-core processor design space evaluation using automatic multi-threaded workload synthesis
The design and evaluation of microprocessor architectures is a difficult and time-consuming task. Although small, handcoded microbenchmarks can be used to accelerate performance e...
Clay Hughes, Tao Li
CASCON
1994
123views Education» more  CASCON 1994»
14 years 11 months ago
Integrating real-time and partial-order information in event-data displays
The events occurring in the execution of a distributed or parallel application are related by a partial, rather than a total, order. We have developed prototype software that coll...
David J. Taylor, Michael H. Coffin
ISSS
2002
IEEE
148views Hardware» more  ISSS 2002»
15 years 2 months ago
A Case Study of Hardware and Software Synthesis in ForSyDe
ForSyDe (FORmal SYstem DEsign) is a methodology which addresses the design of SoC applications which may contain control as well as data flow dominated parts. Starting with a for...
Ingo Sander, Axel Jantsch, Zhonghai Lu
CASES
2005
ACM
14 years 12 months ago
Architectural support for real-time task scheduling in SMT processors
In Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architec...
Francisco J. Cazorla, Peter M. W. Knijnenburg, Riz...
CODES
2005
IEEE
15 years 3 months ago
Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines
The performance of virtual machines (e.g., Java Virtual Machines—JVMs) can be significantly improved when critical code sections (e.g., Java bytecode methods) are migrated from...
Miljan Vuletic, Christophe Dubach, Laura Pozzi, Pa...