744 search results - page 101 / 149 » Software Transactional Memory on Relaxed Memory Models |
HICSS
2009
IEEE
15 years 8 months ago
2009
IEEE
Operating systems were created to provide multiple tasks with access to scarce hardware resources like CPU, memory, or storage. Modern programmable hardware, however, may contain ...
114
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MEMOCODE
2008
IEEE
15 years 8 months ago
2008
IEEE
—Caches are commonly employed to hide the latency gap between memory and the CPU by exploiting locality in memory accesses. The cache performance strongly influences a system’...
109
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SPIN
2009
Springer
15 years 8 months ago
2009
Springer
Abstract. We present a new decision procedure for detecting property violations in pushdown models for concurrent programs that use lock-based synchronization, where each thread’...
CASES
2001
ACM
15 years 5 months ago
2001
ACM
Intertask/interprocess synchronization overheads may be significant in a multiprocessor-shared memory System-on-a-Chip implementation. These overheads are observed in terms of loc...
IEEEIAS
2007
IEEE
15 years 8 months ago
2007
IEEE
This paper introduces a mathematical model, called Team Edit Automata, for evaluating software security properties. We use the model to describe security properties and their corr...