744 search results - page 120 / 149 » Software Transactional Memory on Relaxed Memory Models |
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CODES
2008
IEEE
15 years 6 months ago
2008
IEEE
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
CGO
2009
IEEE
15 years 6 months ago
2009
IEEE
Abstract—Multicore systems have not only become ubiquitous in the desktop and server worlds, but are also becoming the standard in the embedded space. Multicore offers programabi...
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ATVA
2005
Springer
15 years 5 months ago
2005
Springer
Abstract. The Real Time Specification for Java (RTSJ) is an augmentation of Java for real time applications of various degrees of hardness. The central features of RTSJ are real t...
EUROSYS
2010
ACM
15 years 4 months ago
2010
ACM
A complex software system typically has a large number of objects in the memory, holding references to each other to implement an object model. Deciding when the objects should be...
LCTRTS
2004
Springer
15 years 5 months ago
2004
Springer
This paper presents Spinach, a new simulator toolset specifically designed to target programmable network interface architectures. Spinach models both system components that are ...