Sciweavers

744 search results - page 21 / 149
» Software Transactional Memory on Relaxed Memory Models
Sort
View
ISLPED
2010
ACM
158views Hardware» more  ISLPED 2010»
14 years 8 months ago
STM versus lock-based systems: an energy consumption perspective
The shift towards multicore processors and the well-known drawbacks imposed by lock-based synchronization have forced researchers to devise new alternatives for building concurren...
Felipe Klein, Alexandro Baldassin, Joao Moreira, P...
ASPLOS
2011
ACM
14 years 1 months ago
Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory
Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors. Best-effort Hardware Transactional Memory (HTM) designs, such a...
Luke Dalessandro, François Carouge, Sean Wh...
IPPS
2010
IEEE
14 years 7 months ago
Dynamic analysis of the relay cache-coherence protocol for distributed transactional memory
Transactional memory is an alternative programming model for managing contention in accessing shared in-memory data objects. Distributed transactional memory (TM) promises to alle...
Bo Zhang, Binoy Ravindran
EUROSYS
2007
ACM
15 years 1 months ago
Whodunit: transactional profiling for multi-tier applications
This paper is concerned with performance debugging of multitier applications, such as commonly found in servers and dynamic-content web sites. Existing tools and techniques for pr...
Anupam Chanda, Alan L. Cox, Willy Zwaenepoel
IEEEPACT
2009
IEEE
14 years 7 months ago
FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery
Abstract--Version management, one of the key design dimensions of Hardware Transactional Memory (HTM) systems, defines where and how transactional modifications are stored. Current...
Marc Lupon, Grigorios Magklis, Antonio Gonzá...