744 search results - page 38 / 149 » Software Transactional Memory on Relaxed Memory Models |
113
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HPCA
2006
IEEE
16 years 2 months ago
2006
IEEE
Transactional memory (TM) provides an easy-to-use and high-performance parallel programming model for the upcoming chip-multiprocessor systems. Several researchers have proposed a...
DASFAA
2009
IEEE
15 years 8 months ago
2009
IEEE
This paper investigates the problem of writing data to passive RFID tag memory and proposes a reprocessing model for assuring the atomicity and durability of writing transactions i...
124
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ASPLOS
2010
ACM
15 years 8 months ago
2010
ACM
With the right techniques, multicore architectures may be able to continue the exponential performance trend that elevated the performance of applications of all types for decades...
112
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HICSS
1995
IEEE
15 years 5 months ago
1995
IEEE
The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable in...
102
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SYSTOR
2009
ACM
15 years 8 months ago
2009
ACM
Apache is a large-scale industrial multi-process and multithreaded application, which uses lock-based synchronization. We report on our experience in modifying Apache’s cache mo...