744 search results - page 41 / 149 » Software Transactional Memory on Relaxed Memory Models |
145
Voted
TC
2010
14 years 10 months ago
2010
We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator ...
147
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EUROPAR
2010
Springer
15 years 4 months ago
2010
Springer
Abstract. This paper is motivated by the desire to provide an efficient and scalable software cache implementation of OpenMP on multicore and manycore architectures in general, and...
152
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TACAS
1998
Springer
15 years 8 months ago
1998
Springer
This paper enables symbolic ternary simulation of systems with large embedded memories. Each memory array is replaced with a behavioral model, where the number of symbolic variable...
182
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ISCA
1993
IEEE
15 years 7 months ago
1993
IEEE
Advances in circuit and integration technology are continuously boosting the speed of microprocessors. One of the main challenges presented by such developments is the effective u...