Sciweavers

744 search results - page 67 / 149
» Software Transactional Memory on Relaxed Memory Models
Sort
View
ISCAS
2002
IEEE
124views Hardware» more  ISCAS 2002»
15 years 8 months ago
Performance optimization of multiple memory architectures for DSP
Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of archi...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha
ISCA
1999
IEEE
187views Hardware» more  ISCA 1999»
15 years 8 months ago
Area Efficient Architectures for Information Integrity in Cache Memories
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
Seongwoo Kim, Arun K. Somani
SNPD
2003
15 years 5 months ago
Incomplete Information Processing for Optimization of Distributed Applications
This paper focuses on non-strict processing, optimization, and partial evaluation of MPI programs which use incremental data structures (ISs). We describe the design and implement...
Alfredo Cristóbal-Salas, Andrei Tchernykh, ...
DSN
2006
IEEE
15 years 10 months ago
Assessment of the Effect of Memory Page Retirement on System RAS Against Hardware Faults
The Solaris 10 Operating System includes a number of new features for predictive self-healing. One such feature is the ability of the Fault Management software to diagnose memory ...
Dong Tang, Peter Carruthers, Zuheir Totari, Michae...
HOTOS
2007
IEEE
15 years 7 months ago
Automatic Mutual Exclusion
We propose a new concurrent programming model, Automatic Mutual Exclusion (AME). In contrast to lock-based programming, and to other programming models built over software transac...
Michael Isard, Andrew Birrell