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» Software Transactional Memory on Relaxed Memory Models
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POPL
2009
ACM
15 years 10 months ago
The semantics of power and ARM multiprocessor machine code
We develop a rigorous semantics for Power and ARM multiprocessor programs, including their relaxed memory model and the behaviour of reasonable fragments of their instruction sets...
Jade Alglave, Anthony C. J. Fox, Samin Ishtiaq, Ma...
150
Voted
VMCAI
2010
Springer
16 years 1 months ago
Shape Analysis of Low-Level C with Overlapping Structures
Abstract. Device drivers often keep data in multiple data structures simultaneously while embedding list or tree related records into the records containing the actual data; this r...
Jörg Kreiker, Helmut Seidl, Vesal Vojdani
137
Voted
PLDI
2011
ACM
14 years 6 months ago
Understanding POWER multiprocessors
Exploiting today’s multiprocessors requires highperformance and correct concurrent systems code (optimising compilers, language runtimes, OS kernels, etc.), which in turn requir...
Susmit Sarkar, Peter Sewell, Jade Alglave, Luc Mar...
131
Voted
LCTRTS
2010
Springer
15 years 10 months ago
Versatile system-level memory-aware platform description approach for embedded MPSoCs
In this paper, we present a novel system modeling language which targets primarily the development of source-level multiprocessor memory aware optimizations. In contrast to previo...
Robert Pyka, Felipe Klein, Peter Marwedel, Stylian...
127
Voted
OSDI
2008
ACM
16 years 4 months ago
Gadara: Dynamic Deadlock Avoidance for Multithreaded Programs
Deadlock is an increasingly pressing concern as the multicore revolution forces parallel programming upon the average programmer. Existing approaches to deadlock impose onerous bu...
Manjunath Kudlur, Scott A. Mahlke, Stéphane...