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IPPS
2002
IEEE
15 years 11 months ago
Variable Partitioning and Scheduling of Multiple Memory Architectures for DSP
Multiple memory module architecture enjoys higher memory access bandwidth and thus higher performance. Two key problems in gaining high performance in this kind of architecture ar...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha
ISCAS
2002
IEEE
124views Hardware» more  ISCAS 2002»
15 years 11 months ago
Performance optimization of multiple memory architectures for DSP
Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of archi...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
15 years 11 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
LION
2010
Springer
209views Optimization» more  LION 2010»
15 years 11 months ago
Feature Extraction from Optimization Data via DataModeler's Ensemble Symbolic Regression
We demonstrate a means of knowledge discovery through feature extraction that exploits the search history of an optimization run. We regress a symbolic model ensemble from optimiza...
Kalyan Veeramachaneni, Katya Vladislavleva, Una-Ma...
CISIS
2009
IEEE
15 years 11 months ago
Semi-Automatic Annotation System for OWL-Based Semantic Search
—Current keyword search by Google, Yahoo, and so on gives enormous unsuitable results. A solution to this perhaps is to annotate semantics to textual web data to enable semantic ...
C.-H. Liu, H.-C. Chen, J.-L. Jain, J.-Y. Chen
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