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» Software performance engineering of component-based systems
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CODES
2007
IEEE
15 years 11 months ago
Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip
Networks on Chip (NoC) have emerged as the design paradigm for scalable System on Chip communication infrastructure. A growing number of applications, often with firm (FRT) or so...
Andreas Hansson, Martijn Coenen, Kees Goossens
CODES
2006
IEEE
15 years 11 months ago
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...
Martijn Coenen, Srinivasan Murali, Andrei Radulesc...
LCTRTS
2004
Springer
15 years 10 months ago
Finding effective compilation sequences
Most modern compilers operate by applying a fixed, program-independent sequence of optimizations to all programs. Compiler writers choose a single “compilation sequence”, or ...
L. Almagor, Keith D. Cooper, Alexander Grosul, Tim...
PLDI
2003
ACM
15 years 10 months ago
Linear analysis and optimization of stream programs
As more complex DSP algorithms are realized in practice, an increasing need for high-level stream abstractions that can be compiled without sacrificing efficiency. Toward this en...
Andrew A. Lamb, William Thies, Saman P. Amarasingh...
WSC
1997
15 years 6 months ago
A Virtual PNNI Network Testbed
We describe our experiences designing and implementing a virtual PNNI network testbed. The network elements and signaling protocols modeled are consistent with the ATM Forum PNNI ...
Kalyan S. Perumalla, Matthew Andrews, Sandeep N. B...