7027 search results - page 1199 / 1406 » Software process: a roadmap |
145
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ICPP
2003
IEEE
15 years 11 months ago
2003
IEEE
The bus that connects processors to memory is known to be a major architectural bottleneck in SMPs. However, both software and scheduling policies for these systems generally focu...
148
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IOLTS
2003
IEEE
15 years 11 months ago
2003
IEEE
Fault tolerant design is a technique emerging in Integrated Circuits (IC’s) to deal with the increasing error susceptibility (Soft Errors, or Single Event Upsets, SEU) caused by...
163
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IPPS
2003
IEEE
15 years 11 months ago
2003
IEEE
Tiled architectures can provide a model for early estimation of global interconnect costs. A design exploration tool for reconfigurable architectures is currently under developmen...
144
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ITC
2003
IEEE
15 years 11 months ago
2003
IEEE
This paper presents an attempt of using intelligent agents for testing and repairing a distributed system, whose elements may or may not have embedded BIST (Built-In Self-Test) an...
145
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IV
2003
IEEE
15 years 11 months ago
2003
IEEE
In the paper, we suggest a set of visualization-based exploratory tools to support analysis and comparison of different spatial development scenarios, such as results of simulatio...