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DAC
2007
ACM
15 years 5 months ago
Design for Verification in System-level Models and RTL
It has long been the practice to create models in C or C++ for architectural studies, software prototyping and RTL verification in the design of Systems-on-Chip (SoC). It is often...
Anmol Mathur, Venkat Krishnaswamy
FPL
2000
Springer
128views Hardware» more  FPL 2000»
15 years 5 months ago
Verification of Dynamically Reconfigurable Logic
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standa...
David Robinson, Patrick Lysaght
ACSAC
2008
IEEE
15 years 3 months ago
Assessing Quality of Policy Properties in Verification of Access Control Policies
Access control policies are often specified in declarative languages. In this paper, we propose a novel approach, called mutation verification, to assess the quality of properties...
Evan Martin, JeeHyun Hwang, Tao Xie, Vincent C. Hu
BCS
2008
15 years 3 months ago
Tools for Traceable Security Verification
Dependable systems evolution has been identified by the UK Computing Research Committee (UKCRC) as one of the current grand challenges for computer science. We present work toward...
Jan Jürjens, Yijun Yu, Andreas Bauer 0002
ENTCS
2002
145views more  ENTCS 2002»
15 years 1 months ago
Combining Monitors for Runtime System Verification
Runtime verification permits checking system properties that cannot be fully verified off-line. This is particularly true when the system includes complex third-party components, ...
Joshua Levy, Hassen Saïdi, Tomás E. Ur...