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GLOBECOM
2006
IEEE
15 years 3 months ago
Shared-Memory Combined Input-Crosspoint Buffered Packet Switch for Differentiated Services
— Combined input-crosspoint buffered (CICB) packet switches with dedicated crosspoint buffers require a minimum amount of memory in the buffered crossbar of N2 × k × L, where N...
Ziqian Dong, Roberto Rojas-Cessa
CANPC
1999
Springer
15 years 2 months ago
Implementing Application-Specific Cache-Coherence Protocols in Configurable Hardware
Streamlining communication is key to achieving good performance in shared-memory parallel programs. While full hardware support for cache coherence generally offers the best perfo...
David Brooks, Margaret Martonosi
ISCA
2007
IEEE
146views Hardware» more  ISCA 2007»
15 years 4 months ago
Virtual hierarchies to support server consolidation
Server consolidation is becoming an increasingly popular technique to manage and utilize systems. This paper develops CMP memory systems for server consolidation where most sharin...
Michael R. Marty, Mark D. Hill
SC
1995
ACM
15 years 1 months ago
Architectural Mechanisms for Explicit Communication in Shared Memory Multiprocessors
The goal of this work is to explore architectural mechanisms for supporting explicit communication in cachecoherent shared memory multiprocessors. The motivation stems from the ob...
Umakishore Ramachandran, Gautam Shah, Anand Sivasu...
ASPLOS
2009
ACM
15 years 10 months ago
DMP: deterministic shared memory multiprocessing
Current shared memory multicore and multiprocessor systems are nondeterministic. Each time these systems execute a multithreaded application, even if supplied with the same input,...
Joseph Devietti, Brandon Lucia, Luis Ceze, Mark Os...