Sciweavers

230 search results - page 28 / 46
» Software-Extended Coherent Shared Memory: Performance and Co...
Sort
View
ASPLOS
2012
ACM
13 years 5 months ago
Scalable address spaces using RCU balanced trees
Software developers commonly exploit multicore processors by building multithreaded software in which all threads of an application share a single address space. This shared addre...
Austin T. Clements, M. Frans Kaashoek, Nickolai Ze...
SPDP
1993
IEEE
15 years 1 months ago
The Meerkat Multicomputer
Meerkat is a distributed memory multicomputer architecture that scales to hundreds of processors. Meerkat uses a two dimensional passive backplane to connect nodes composed of pro...
Robert C. Bedichek, Curtis Brown
SIGMETRICS
2004
ACM
103views Hardware» more  SIGMETRICS 2004»
15 years 3 months ago
Myths and realities: the performance impact of garbage collection
This paper explores and quantifies garbage collection behavior for three whole heap collectors and generational counterparts: copying semi-space, mark-sweep, and reference counti...
Stephen M. Blackburn, Perry Cheng, Kathryn S. McKi...
CODES
2007
IEEE
15 years 4 months ago
Predator: a predictable SDRAM memory controller
Memory requirements of intellectual property components (IP) in contemporary multi-processor systems-on-chip are increasing. Large high-speed external memories, such as DDR2 SDRAM...
Benny Akesson, Kees Goossens, Markus Ringhofer
CF
2006
ACM
15 years 1 months ago
An efficient cache design for scalable glueless shared-memory multiprocessors
Traditionally, cache coherence in large-scale shared-memory multiprocessors has been ensured by means of a distributed directory structure stored in main memory. In this way, the ...
Alberto Ros, Manuel E. Acacio, José M. Garc...