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» Software-Only Bus Encoding Techniques for an Embedded System
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ISSS
1998
IEEE
87views Hardware» more  ISSS 1998»
15 years 1 months ago
Instruction Encoding Techniques for Area Minimization of Instruction ROM
In this paper, we propose instruction encoding techniques for embedded system design, which encode immediate fields of instructions to reduce the size of an instruction memory. Al...
Takanori Okuma, Hiroyuki Tomiyama, Akihiko Inoue, ...
CEC
2003
IEEE
15 years 2 months ago
An evolutionary approach for reducing the switching activity in address buses
In this paper we present two new approaches based on genetic algorithms (GA) to reduce power consumption by communication buses in an embedded system. The first approach makes it ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
DATE
2000
IEEE
90views Hardware» more  DATE 2000»
15 years 1 months ago
Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design
We present a technique for fast estimation of the power consumed by the cache and bus sub-system of a parameterized system-on-a-chip design for a given application. The technique ...
Jörg Henkel, Tony Givargis, Frank Vahid
DAC
2005
ACM
14 years 11 months ago
Sign bit reduction encoding for low power applications
This paper proposes a low power technique, called SBR (Sign Bit Reduction) which may reduce the switching activity in multipliers as well as data buses. Utilizing the multipliers ...
M. Saneei, Ali Afzali-Kusha, Zainalabedin Navabi
RTSS
2008
IEEE
15 years 3 months ago
Hardware Runtime Monitoring for Dependable COTS-Based Real-Time Embedded Systems
COTS peripherals are heavily used in the embedded market, but their unpredictability is a threat for high-criticality real-time systems: it is hard or impossible to formally verif...
Rodolfo Pellizzoni, Patrick O'Neil Meredith, Marco...