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DFT
2003
IEEE
113views VLSI» more  DFT 2003»
15 years 4 months ago
Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
73
Voted
ASPDAC
2005
ACM
119views Hardware» more  ASPDAC 2005»
15 years 26 days ago
CMP aware shuttle mask floorplanning
- By putting different chips on the same mask, shuttle mask (or multiple project wafer) provides an economical solution for low volume designs and design prototypes to share the ri...
Gang Xu, Ruiqi Tian, David Z. Pan, Martin D. F. Wo...
EDOC
2007
IEEE
15 years 2 months ago
Automated Model-Based Configuration of Enterprise Java Applications
The decentralized process of configuring enterprise applications is complex and error-prone, involving multiple participants/roles and numerous configuration changes across multipl...
Jules White, Douglas C. Schmidt, Krzysztof Czarnec...
83
Voted
GECCO
2008
Springer
129views Optimization» more  GECCO 2008»
14 years 12 months ago
Exploiting the path of least resistance in evolution
Hereditary Repulsion (HR) is a selection method coupled with a fitness constraint that substantially improves the performance and consistency of evolutionary algorithms. This als...
Gearoid Murphy, Conor Ryan
80
Voted
DCOSS
2009
Springer
15 years 5 months ago
Cheap or Flexible Sensor Coverage
We consider dual classes of geometric coverage problems, in which disks, corresponding to coverage regions of sensors, are used to cover a region or set of points in the plane. The...
Amotz Bar-Noy, Theodore Brown, Matthew P. Johnson,...