Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
- By putting different chips on the same mask, shuttle mask (or multiple project wafer) provides an economical solution for low volume designs and design prototypes to share the ri...
Gang Xu, Ruiqi Tian, David Z. Pan, Martin D. F. Wo...
The decentralized process of configuring enterprise applications is complex and error-prone, involving multiple participants/roles and numerous configuration changes across multipl...
Jules White, Douglas C. Schmidt, Krzysztof Czarnec...
Hereditary Repulsion (HR) is a selection method coupled with a fitness constraint that substantially improves the performance and consistency of evolutionary algorithms. This als...
We consider dual classes of geometric coverage problems, in which disks, corresponding to coverage regions of sensors, are used to cover a region or set of points in the plane. The...
Amotz Bar-Noy, Theodore Brown, Matthew P. Johnson,...