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DFT
2003
IEEE
113views VLSI» more  DFT 2003»
15 years 9 months ago
Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
INFOCOM
2003
IEEE
15 years 9 months ago
Optimal replacement policies for non-uniform cache objects with optional eviction
Abstract— Replacement policies for general caching applications and Web caching in particular have been discussed extensively in the literature. Many ad-hoc policies have been pr...
Omri Bahat, Armand M. Makowski
INFOCOM
2003
IEEE
15 years 9 months ago
Optimal Bandwidth Reservation Schedule in Cellular Network
Abstract— Efficient bandwidth allocation strategy with simultaneous fulfillment of QoS requirement of a user in a mobile cellular network is still a critical and an important p...
Samrat Ganguly, B. R. Badrinath, Navin Goyal
DATE
2002
IEEE
123views Hardware» more  DATE 2002»
15 years 9 months ago
False Path Elimination in Quasi-Static Scheduling
We have developed a technique to compute a Quasi Static Schedule of a concurrent specification for the software partition of an embedded system. Previous work did not take into a...
G. Arrigoni, L. Duchini, Claudio Passerone, Lucian...
DATE
1999
IEEE
162views Hardware» more  DATE 1999»
15 years 8 months ago
MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis
In this paper, we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrate...
Robert P. Dick, Niraj K. Jha