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DAC
2009
ACM
15 years 5 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
75
Voted
TCOM
2010
91views more  TCOM 2010»
14 years 9 months ago
Robust Power Allocation Algorithms for Wireless Relay Networks
—Resource allocation promises significant benefits in wireless networks. In order to fully reap these benefits, it is important to design efficient resource allocation algori...
Tony Q. S. Quek, Moe Z. Win, Marco Chiani
EWSN
2004
Springer
15 years 10 months ago
Design of Surveillance Sensor Grids with a Lifetime Constraint
A surveillance area is to be monitored using a grid network of heterogeneous sensor nodes. There are two types of nodes; type 0 nodes which perform sensing and relaying of data wit...
Vivek Mhatre, Catherine Rosenberg, Daniel Kofman, ...
SIGMETRICS
2008
ACM
140views Hardware» more  SIGMETRICS 2008»
14 years 11 months ago
Scalable VPN routing via relaying
Enterprise customers are increasingly adopting MPLS (Multiprotocol Label Switching) VPN (Virtual Private Network) service that offers direct any-to-any reachability among the cust...
Changhoon Kim, Alexandre Gerber, Carsten Lund, Dan...
184
Voted
DAC
2011
ACM
13 years 11 months ago
Efficient incremental analysis of on-chip power grid via sparse approximation
In this paper, a new sparse approximation technique is proposed for incremental power grid analysis. Our proposed method is motivated by the observation that when a power grid net...
Pei Sun, Xin Li, Ming Yuan Ting