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ICCAD
2003
IEEE
219views Hardware» more  ICCAD 2003»
15 years 7 months ago
A Min-Cost Flow Based Detailed Router for FPGAs
Routing for FPGAs has been a very challenging problem due to the limitation of routing resources. Although the FPGA routing problem has been researched extensively, most algorithm...
Seokjin Lee, Yongseok Cheon, Martin D. F. Wong
FPGA
2003
ACM
137views FPGA» more  FPGA 2003»
15 years 3 months ago
Customized regular channel design in FPGAs
FPGAs are one of the essential components in platform-based embedded systems. Such systems are customized and applied only to a limited set of applications. Also some applications...
Elaheh Bozorgzadeh, Majid Sarrafzadeh
CODES
2005
IEEE
15 years 3 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
ESANN
2008
14 years 11 months ago
Neural network hardware architecture for pattern recognition in the HESS2 project
In this paper, we consider the problem of implementation of neural network in the context of the level 2 trigger of HESS2 project. We propose a hardware architecture which which ta...
Narayanan Ramanan, Sonia Khatchadourian, Jean-Chri...
79
Voted
ITC
1998
IEEE
104views Hardware» more  ITC 1998»
15 years 2 months ago
Built-in self-test of FPGA interconnect
: We introduce the first BIST approach for testing the programmable routing network in FPGAs. Our method detects opens in, and shorts among, wiring segments, and also faults affect...
Charles E. Stroud, Sajitha Wijesuriya, Carter Hami...