354 search results - page 23 / 71 » Sorting networks on FPGAs |
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Voted
BIOADIT
2004
Springer
15 years 3 months ago
2004
Springer
Abstract. In this paper we present a functional model of a spiking neuron intended for hardware implementation. Some features of biological spiking neuabstracted, while preserving ...
CEC
2007
IEEE
15 years 4 months ago
2007
IEEE
— In this paper, a neural network approach is presented to expand the Pareto-optimal front for multiobjective optimization problems. The network is trained using results obtained...
SAMOS
2007
Springer
15 years 4 months ago
2007
Springer
—Current FPGAs provide a powerful platform for network processing applications. The main challenge is the exploitation of the reconfiguration to increase the performance of the s...
FPL
2008
Springer
14 years 12 months ago
2008
Springer
While there have been many reported implementations of Networks-on-Chip (NoCs) on FPGAs, they have not seen the same acceptance as NoCs on ASICs. One reason is that communication ...
FPL
2008
Springer
14 years 12 months ago
2008
Springer
Abstract-The network on chip will become a future general purpose interconnect for FPGAs much like today's standard OPB or PLB bus architectures. However, performance characte...