19 search results - page 1 / 4 » Source-Level Timing Annotation and Simulation for a Heteroge... |
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
A generic and retargetable tool flow is presented that enables the export of timing data from software running on a cycle-accurate Virtual Prototype (VP) to a concurrent function...
DAC
2004
ACM
15 years 10 months ago
2004
ACM
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
143
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PDP
2011
IEEE
14 years 1 months ago
2011
IEEE
—Energy-efficiency is becoming one of the most critical issues in embedded system design. In Network-on-Chip (NoC) based heterogeneous Multiprocessor Systems, the energy consump...
88
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DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
86
Voted
CODES
2004
IEEE
15 years 1 months ago
2004
IEEE
Single chip heterogeneous multiprocessors are arising to meet the computational demands of portable and handheld devices. These computing systems are not fully custom designs trad...