—With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bankinterleave...
In this paper a general framework for separation logic inside the HOL theorem prover is presented. This framework is based on Abeparation Logic. It contains a model of an abstract,...
In this paper, we provide a systematic comparison of various evolutionary approaches to multiobjective optimization using six carefully chosen test functions. Each test function i...
This paper reports our experiences on the Scalable Network Of Workstation (SNOW) project, which implements a novel methodology to support user-level process migration for traditio...
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...