23 search results - page 1 / 5 » Sparse Matrix-Vector multiplication on FPGAs |
79
Voted
FCCM
2006
IEEE
15 years 5 months ago
2006
IEEE
We present an architecture and an implementation of an FPGA-based sparse matrix-vector multiplier (SMVM) for use in the iterative solution of large, sparse systems of equations ar...
FCCM
2007
IEEE
15 years 20 days ago
2007
IEEE
Creating a high throughput sparse matrix vector multiplication (SpMxV) implementation depends on a balanced system design. In this paper, we introduce the innovative SpMxV Solver ...
103
Voted
FPGA
2005
ACM
15 years 4 months ago
2005
ACM
Floating-point Sparse Matrix-Vector Multiplication (SpMXV) is a key computational kernel in scientific and engineering applications. The poor data locality of sparse matrices sig...
103
click to vote
ERSA
2010
14 years 9 months ago
2010
Cache-based, general purpose CPUs perform at a small fraction of their maximum floating point performance when executing memory-intensive simulations, such as those required for sp...
103
Voted
CATA
2010
15 years 10 days ago
2010
Computations with sparse matrices on "multicore cache based" computers are affected by the irregularity of the problem at hand, and performance degrades easily. In this ...