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FCCM
2006
IEEE
108views VLSI» more  FCCM 2006»
15 years 3 months ago
A Reconfigurable Distributed Computing Fabric Exploiting Multilevel Parallelism
This paper presents a novel reconfigurable data flow processing architecture that promises high performance by explicitly targeting both fine- and course-grained parallelism. This...
Charles L. Cathey, Jason D. Bakos, Duncan A. Buell
ICPP
1998
IEEE
15 years 1 months ago
The Postal Network: A Versatile Interconnection Topology
The postal network is an interconnection network that possesses many desirable properties which are important in network design and applications. It includes hypercubes and Fibona...
Jie Wu, Yuanyuan Yang
CCGRID
2005
IEEE
15 years 3 months ago
n-Cycle: a set of algorithms for task distribution on a commodity grid
— The global internet is rich in commodity resources but scarce in specialized resources. We argue that a grid framework can achieve better performance if it separates management...
Ladislau Bölöni, Damla Turgut, Dan C. Ma...
IPPS
1999
IEEE
15 years 2 months ago
Application of Parallel Processors to Real-Time Sensor Array Processing
Historically, most radar sensor array processing has been implemented using dedicated and specialized processing systems. This approach was necessary because the algorithm computa...
David R. Martinez
ICPP
2009
IEEE
15 years 4 months ago
Speeding Up Distributed MapReduce Applications Using Hardware Accelerators
—In an attempt to increase the performance/cost ratio, large compute clusters are becoming heterogeneous at multiple levels: from asymmetric processors, to different system archi...
Yolanda Becerra, Vicenç Beltran, David Carr...