18 search results - page 1 / 4 » Specialized Dynamic Optimizations for High-Performance Energ... |
82
Voted
CGO
2004
IEEE
15 years 1 months ago
2004
IEEE
We study several major characteristics of dynamic optimization within the PARROT power-aware, trace-cachebased microarchitectural framework. We investigate the benefit of providin...
ICCD
2007
IEEE
15 years 7 months ago
2007
IEEE
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...
ISLPED
2010
ACM
14 years 10 months ago
2010
ACM
The on-chip memory is a dominant source of power and energy consumption in modern and future processors. This paper explores the use of a new emerging non-volatile memory technolo...
119
Voted
TVLSI
2010
14 years 4 months ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
113
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CORR
2010
Springer
14 years 7 months ago
2010
Springer
Energy consumption is a critical design issue in real-time systems, especially in battery- operated systems. Maintaining high performance, while extending the battery life between...