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CODES
2003
IEEE
15 years 8 months ago
A codesigned on-chip logic minimizer
Boolean logic minimization is traditionally used in logic synthesis tools running on powerful desktop computers. However, logic minimization has recently been proposed for dynamic...
Roman L. Lysecky, Frank Vahid
FCCM
2003
IEEE
113views VLSI» more  FCCM 2003»
15 years 8 months ago
Issues and Approaches to Coarse-Grain Reconfigurable Architecture Development
Although domain-specialized FPGAs can offer significant area, speed and power improvements over conventional reconfigurable devices, there are several unique and unexplored design...
Kenneth Eguro, Scott Hauck
137
Voted
GLVLSI
2003
IEEE
202views VLSI» more  GLVLSI 2003»
15 years 8 months ago
System level design of real time face recognition architecture based on composite PCA
Design and implementation of a fast parallel architecture based on an improved principal component analysis (PCA) method called Composite PCA suitable for real-time face recogniti...
Rajkiran Gottumukkal, Vijayan K. Asari
GLVLSI
2003
IEEE
171views VLSI» more  GLVLSI 2003»
15 years 8 months ago
Combining wire swapping and spacing for low-power deep-submicron buses
We propose an approach for reducing the energy consumption of address buses that targets both the switching and the crosstalk components of power dissipation. The method is based ...
Enrico Macii, Massimo Poncino, Sabino Salerno
GLVLSI
2003
IEEE
129views VLSI» more  GLVLSI 2003»
15 years 8 months ago
A system-level methodology for fast multi-objective design space exploration
In this paper, we address the problem of the efficient exploration of the architectural design space for parameterized systems. Since the design space is multi-objective, our aim ...
Gianluca Palermo, Cristina Silvano, S. Valsecchi, ...