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HVC
2007
Springer
153views Hardware» more  HVC 2007»
13 years 10 months ago
On the Architecture of System Verification Environments
Implementations of computer systems comprise many layers and employ a variety of programming languages. Building such systems requires support of an often complex, accompanying too...
Mark A. Hillebrand, Wolfgang J. Paul
PLPV
2010
ACM
13 years 8 months ago
Challenge benchmarks for verification of real-time programs
Real-time systems, and in particular safety-critical systems, are a rich source of challenges for the program verification community as software errors can have catastrophic conse...
Tomás Kalibera, Pavel Parizek, Ghaith Hadda...
FDL
2007
IEEE
14 years 25 days ago
Automatic High Level Assertion Generation and Synthesis for Embedded System Design
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
Lun Li, Frank P. Coyle, Mitchell A. Thornton
ICSE
2008
IEEE-ACM
14 years 6 months ago
Security protocols, properties, and their monitoring
This paper examines the suitability and use of runtime verification as means for monitoring security protocols and their properties. In particular, we employ the runtime verificat...
Andreas Bauer 0002, Jan Jürjens
CAISE
2006
Springer
13 years 10 months ago
Modelling and Verifying of e-Commerce Systems
Static function hierarchies and models of the dynamic behaviour are typically used in e-commerce systems. Issues to be verifies are the completeness and correctness of the static f...
Andreas Speck