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» Specification and Verification of Model Transformations Usin...
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105
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DAC
1994
ACM
15 years 4 months ago
Error Diagnosis for Transistor-Level Verification
This paper describes a diagnosis technique for locating design errors in circuit implementations which do not match their functional specification. The method efficiently propagat...
Andreas Kuehlmann, David Ihsin Cheng, Arvind Srini...
130
Voted
FMCAD
2008
Springer
15 years 2 months ago
Word-Level Sequential Memory Abstraction for Model Checking
el Sequential Memory Abstraction for Model Checking Per Bjesse Advanced Technology Group Synopsys Inc. Many designs intermingle large memories with wide data paths and nontrivial c...
Per Bjesse
109
Voted
SIGSOFT
2006
ACM
16 years 1 months ago
SYNERGY: a new algorithm for property checking
We consider the problem if a given program satisfies a specified safety property. Interesting programs have infinite state spaces, with inputs ranging over infinite domains, and f...
Bhargav S. Gulavani, Thomas A. Henzinger, Yamini K...
109
Voted
ICPR
2008
IEEE
16 years 1 months ago
3D Shape Context and Distance Transform for action recognition
We propose the use of 3D (2D+time) Shape Context to recognize the spatial and temporal details inherent in human actions. We represent an action in a video sequence by a 3D point ...
Franziska Meier, Irfan A. Essa, Matthias Grundmann
109
Voted
ICCAD
2009
IEEE
159views Hardware» more  ICCAD 2009»
14 years 10 months ago
First steps towards SAT-based formal analog verification
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
Saurabh K. Tiwary, Anubhav Gupta, Joel R. Phillips...