159 search results - page 9 / 32 » Specifying Proof Systems in Linear Logic with Subexponential... |
SAC
2010
ACM
14 years 7 months ago
2010
ACM
Verification conditions (VCs) are logical formulae whose validity implies the correctness of a program with respect to a specification. The technique of checking software properti...
114
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FMCO
2004
Springer
15 years 3 months ago
2004
Springer
Abstract. A temporal logic is proposed as a tool for specifying properties of Klaim programs. Klaim is an experimental programming language that supports a programming paradigm whe...
109
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ESOP
2006
Springer
15 years 1 months ago
2006
Springer
This paper presents a new program logic designed for facilitating automated reasoning about pointer programs. The program logic is directly inspired by previous work by O'Hea...
CORR
2010
Springer
14 years 9 months ago
2010
Springer
Dependently typed -calculi such as the Logical Framework (LF) are capable of representing relationships between terms through types. By exploiting the "formulas-as-types"...
114
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ACOM
2006
Springer
15 years 3 months ago
2006
Springer
Abstract. This paper explores the use of temporal logics in the context of communication protocols for multiagent systems. We concentrate on frameworks where protocols are used to ...