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SP
2003
IEEE
121views Security Privacy» more  SP 2003»
14 years 21 days ago
Specifying and Verifying Hardware for Tamper-Resistant Software
We specify a hardware architecture that supports tamper-resistant software by identifying an “idealized” hich gives the abstracted actions available to a single user program. ...
David Lie, John C. Mitchell, Chandramohan A. Thekk...
AOSD
2009
ACM
14 years 2 months ago
Modelling hardware verification concerns specified in the e language: an experience report
e is an aspect-oriented hardware verification language that is widely used to verify the design of electronic circuits through the development and execution of testbenches. In rec...
Darren Galpin, Cormac Driver, Siobhán Clark...
SIGPLAN
2002
13 years 7 months ago
On-the-fly model checking from interval logic specifications
Future Interval Logic (FIL) and its intuitive graphical representation, Graphical Interval Logic (GIL), can be used as the formal description language of model checking tools to v...
Miguel J. Hornos, Manuel I. Capel
ICECCS
2002
IEEE
106views Hardware» more  ICECCS 2002»
14 years 11 days ago
Validating Run-time Interactions in Distributed Java Applications
Distributed Java applications represent a large growth area in software. Validating such applications using information from runtime interactions is a challenge. We propose techni...
Sudipto Ghosh, Nishant Bawa, Sameer Goel, Raghu Re...
RSP
2003
IEEE
176views Control Systems» more  RSP 2003»
14 years 21 days ago
Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment
This paper describes the early analysis and estimation features currently implemented in the Berkeley Emulation Engine (BEE) system. BEE is an integrated rapid prototyping and des...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, A...