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PSTV
1993
123views Hardware» more  PSTV 1993»
15 years 2 months ago
On the Verification of Temporal Properties
We present a new algorithm that can be used for solving the model−checking problem for linear−time temporal logic. This algorithm can be viewed as the combination of two exist...
Patrice Godefroid, Gerard J. Holzmann
VLSISP
2008
111views more  VLSISP 2008»
15 years 1 months ago
Design Methodology for Throughput Optimum Architectures of Hash Algorithms of the MD4-class
Abstract. In this paper we propose an architecture design methodology to optimize the throughput of MD4-based hash algorithms. The proposed methodology includes an iteration bound ...
Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede
INFOVIS
2000
IEEE
15 years 6 months ago
Visualizing Massive Multi-Digraphs
We describe MGV, an integrated visualization and exploration system for massive multi-digraph navigation. MGV’s only assumption is that the vertex set of the underlying digraph ...
James Abello, Jeffrey L. Korn
WAOA
2004
Springer
107views Algorithms» more  WAOA 2004»
15 years 7 months ago
Order-Preserving Transformations and Greedy-Like Algorithms
Borodin, Nielsen and Rackoff [5] proposed a framework for ing the main properties of greedy-like algorithms with emphasis on scheduling problems, and Davis and Impagliazzo [6] ext...
Spyros Angelopoulos
ASPDAC
2004
ACM
113views Hardware» more  ASPDAC 2004»
15 years 5 months ago
Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction
- Minimum area is one of the important objectives in technology mapping for lookup table-based FPGAs. It has been proven that the problem is NP-complete. This paper presents a poly...
Chi-Chou Kao, Yen-Tai Lai