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FASE
2009
Springer
15 years 5 months ago
HAVE: Detecting Atomicity Violations via Integrated Dynamic and Static Analysis
Abstract. The reality of multi-core hardware has made concurrent programs pervasive. Unfortunately, writing correct concurrent programs is difficult. Atomicity violation, which is ...
Qichang Chen, Liqiang Wang, Zijiang Yang, Scott D....
DATE
2010
IEEE
131views Hardware» more  DATE 2010»
15 years 4 months ago
Energy-performance design space exploration in SMT architectures exploiting selective load value predictions
—This paper presents a design space exploration of a selective load value prediction scheme suitable for energyaware Simultaneous Multi-Threaded (SMT) architectures. A load value...
Arpad Gellert, Gianluca Palermo, Vittorio Zaccaria...
ICPP
2002
IEEE
15 years 4 months ago
Out-of-Order Instruction Fetch Using Multiple Sequencers
Conventional instruction fetch mechanisms fetch contiguous blocks of instructions in each cycle. They are difficult to scale since taken branches make it hard to increase the siz...
Paramjit S. Oberoi, Gurindar S. Sohi
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
15 years 4 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
APCSAC
2000
IEEE
15 years 3 months ago
Micro-Threading: A New Approach to Future RISC
This paper briefly reviews the current research into RISC microprocessor architecture, which now seems to be so complex as to make the acronym somewhat of an oxymoron. In response...
Chris R. Jesshope, Bing Luo